高等數位積體電路設計 開課單位： 資訊工程研究所(Graduate Institute of Computer Science and Information Engineering) 課程名稱(英文) Advanced Digital Integrated Circuits Design 課程代碼 4105567_01 授課教師： 鍾菁哲 學分數 3 必/選修 選修 開課年級 研究所 先修科目或先備能力： 1. Introduction to Digital Systems
課程概述： This course aims to convey the senior and graduate EE students techniques to design Mixed-Signal IC using current EDA tools. In addition to learning EDA tools for SPICE and HDL co-simulation environment, all-digital PLL/DLL design techniques will also be addressed and take as design examples. Upon completion of the course, the student will be able to design their chip with Mixed-Signal blocks.
學習目標： 1. Understanding the design challenges in mixed-signal IC design
2. Understanding the mixed-signal IC simulation and design flow
3. Understanding how to design the all-digital PLL/DLL
教科書：
課程大綱 分配時數 核心能力 備註 單元主題 內容綱要 講授 示範 隨堂作業 其他 課程大綱介紹與上課進行方式解說 3 Introduction to Mixed-Signal IC Design Flow 3 Introduction to PLL/DLL 3 All-digital PLL Building Blocks (Digital Controlled Oscillator, Phase/Frequency Detector, Frequency Divider, PLL Controller, Loop Filter, PLL Loop Simulation) 3 All-digital PLL Building Blocks (Digital Controlled Oscillator, Phase/Frequency Detector, Frequency Divider, PLL Controller, Loop Filter, PLL Loop Simulation) 3 All-digital PLL Building Blocks (Digital Controlled Oscillator, Phase/Frequency Detector, Frequency Divider, PLL Controller, Loop Filter, PLL Loop Simulation) 3 All-digital PLL Building Blocks (Digital Controlled Oscillator, Phase/Frequency Detector, Frequency Divider, PLL Controller, Loop Filter, PLL Loop Simulation) 3 All-digital DLL Building Blocks (Digital Controlled Delay Line, Phase Detector and Time-to-Digital Converter, DLL Controller and DLL Loop Simulation, Multi-phase Clock Generation) 3 All-digital DLL Building Blocks (Digital Controlled Delay Line, Phase Detector and Time-to-Digital Converter, DLL Controller and DLL Loop Simulation, Multi-phase Clock Generation) 3 Digital Blocks Design (Digital Modeling with Verilog) 3 Analog Blocks Design (Circuit Simulation with HSPICE, Fast-SPICE Full-Chip Simulation with UltraSIM) 3 AMS Simulation Flow (AMS Simulator (AMS-Ultra) and Virtuoso Platform, Prepare for AMS Simulation, AMS Simulation Flow) 3 Low-Voltage All-Digital Phase-Locked Loop 3 On-Chip Oscillators 3 3D-IC Clock Synchronization and Duty-Cycle Correction Circuit 3 Final Project: Design an All-Digital Phase-Locked Loop (1/2) 3 Final Project: Design an All-Digital Phase-Locked Loop (2/2) 3 Final-Term Exam 3
教育目標 1.具獨立從事學術研究或產品創新研發之人才 2.具團隊合作精神及科技整合能力，並在團隊中扮演領導、規劃、管理之角色 3.具自我挑戰與終身學習能力之人才 4.具有學術倫理、工程倫理、國際觀之人才 核心能力 1.具有資訊工程與科學領域之專業知識(Competence in computer science and computer engineering.) 2.具有創新思考、問題解決、獨立研究之能力(Be creative and be able to solve problems and to perform independent research.) 3.具有撰寫中英文專業論文及簡報之能力(Demonstrate good written, oral, and communication skills, in both Chinese and English.) 4.具策劃及執行專題研究之能力(Be able to plan and execute projects.) 5.具有溝通、協調、整合及進行跨領域團隊合作之能力(Have communication, coordination, integration skills and teamwork in multi-disciplinary settings.) 6.具有終身學習與因應資訊科技快速變遷之能力(Recognize the need for, and have the ability to engage in independent and life-long learning.) 7.認識並遵循學術與工程倫理(Understand and commit to academic and professional ethics.) 8.具國際觀及科技前瞻視野(Have international view and vision of future technology.)
教學要點概述： 1. 教材編選(可複選)： 2. 教學方法(可複選)： 3. 評量工具(可複選)： 4. 教學資源： 5. 教學相關配合事項： 1. 本學期課程為遠距教學，每週規定的錄影檔進度要按進度聽完。 2. 本課程以錄影檔授課方式為主，有線上 Gather Town 教室師生互動和 Ecourse2發問平台，無法接受這樣的教學方式的同學